1. Field of the Invention
The present invention relates to a data multiplexing apparatus and method for assembling a plurality of programs of coded video and audio data into packets and multiplexing the packets into a single bit stream.
2. Description of Related Art
Recently, the digital satellite broadcasting systems have been prevailing in which a transmitting side uses the techniques of information compression and multiplexing as in the MPEG (Moving Picture coding Experts Group) 2 or the like to code and multiplex a plurality of programs of quality video and audio information into a single bit stream within in a limited transmission band and transmit the bit stream to a receiving side which disassembles and decode the received bit stream.
At the transmitting side, the video and audio information is coded as in the MPEG2, the digital coded data is multiplexed into a bit stream, the bit stream is subjected to an error correction and modulation, and then transmitted towards a communication satellite from a transmission antenna.
The multiplexer used at the transmitting side is configured as schematically shown in FIG. 1. Briefly, the multiplexer disassembles an elementary stream packetized by an encoder provided upstream thereof, namely, a packetized elementary stream (will be referred to as xe2x80x9cPESxe2x80x9d hereinunder) 101 into transport packets in relatively short transmission units of 188 bytes, and connects a plurality of transport packets by time-division multiplexing to provide a transport stream (will be referred to as xe2x80x9cTSxe2x80x9d hereinunder) 120.
Three PES streams 101, for example, supplied from three encoders are stored into an input controller 103. The input controller 103 supplies three multiplex buffers 1021, 1022 and 1023 with three input PES streams 101, respectively, acquire information of PES headers and ES headers of video and audio data, and supplies a channel selection controller 116 with a synchronization control information.
The multiplex buffers 1021, 1022 and 1023 are each of an FIFO type to provisionally store three PES streams 101, respectively. In these multiplex buffers 1021, 1022 and 1023, the three PES streams 101 are packetized as transport packets (will be referred to as xe2x80x9cTPxe2x80x9d hereinunder) and kept there until they are multiplexed.
The multiplexer includes also a control data generator 105 which generates and packetizes program specific information (will be referred to as xe2x80x9cPSIxe2x80x9d hereinunder) necessary for selection and decoding of a program at the receiving side and service information (will be referred to as xe2x80x9cSIxe2x80x9d hereinunder) on the whole or a part of a program. In some cases, the control data generator 105 uses a system time generated from a basic clock inside the multiplexer to generate a program clock reference (will be referred to as xe2x80x9cPCRxe2x80x9d hereinunder) peculiar to each program and which is used as a reference. A transmission period is managed for each control data, a multiplex request for each control data is sent to the channel selection controller 113 at a time when a control data has to be transmitted while a TP packets for the control data are kept in an output register included in the control data generator 105
The multiplexer further includes a null packet generator 106 which generates, at a time when it is not necessary to multiplex the PES and control data, a TP packet as a code which is meaningless as a data but fills voids in the bit stream.
A TP header generator 109 is also provided in the multiplexer to generate a TP header which has to be multiplexed before the three PES streams 101 are read from the multiplex buffers 1021 1022 and 1023 for multiplexing.
The channel selection controller 113 determines which code should be selected for one of the channels to the control data generator 105, multiplex buffers 1021, 1022 and 1023 and null packet generator 106, and sends a selection signal to a switch 114 to control the multiplex channels. When any one of the multiplex buffers 1021, 1022 and 1023 is selected, the switch 114 is controlled to read from the TP header generator 109 before reading from the multiplex buffers 1021, 1022 and 1023. For reading from the TP header generator 109, the switch 114 is provided with a one of parameters stated in the TP header and which varies depending upon a channel over which the reading is to be done and a timing at which the reading is to be done. The parameters thus delivered to the switch 114 include a packet ID (will be referred to as xe2x80x9cPIDxe2x80x9d hereinunder), adaptation field control signal, etc. A code multiplexed by the switch 114 is delivered as a TP code to a presentation time stamp (will be referred to as xe2x80x9cPTSxe2x80x9d hereinunder)/decoding time stamp (will be referred to as xe2x80x9cDTSxe2x80x9d hereinunder) controller 116 also included in the multiplexer.
The PTS/DTS controller 116 swaps a PTS and DTS of a program being multiplexing between them when the PTS and DTS are not suitable for the PCR for the program, and sends it to an output controller 119 also included in the multiplexer. For example, when a PCR is generated from a value of a system time the multiplexer has, the input controller 103 acquires an elementary stream clock reference (will be referred to as xe2x80x9cESCRxe2x80x9d hereinunder) along with a PTS and DTS, clarifies the topological relation with the ESCR, and replaces it with the PTS and DTS having a correct topological relation with a PCR which is actually sent.
The output controller 119 reads and delivers a TS stream 120 at a time based on the system clock the multiplexer has.
The TS stream 120 should be a bit stream with which all code buffers the decoders have can operate successfully or without failure. Normally, the encoder to implement the coding as in the MPEG2 generates a bit stream with which all the buffers in a transport stream system target decoder (will be referred to as xe2x80x9cT-STDxe2x80x9d hereinunder) can work without failure.
However, in the multiplexer shown in FIG. 1, namely, in the multiplexer disassembling a PES stream 101 into TP packets in relatively short transmission units of 188 bytes, and connecting a plurality of TP packets by time-division multiplexing to provide a TS 120, each buffer of the T-STD is not completely assured for normal operation. If the delay in a multiplex buffer 102 for a certain channel, for example, is larger for any reason, the virtual buffer in the T-STD is likely to fail.
If a code topological relation an input stream inherently has and which is appropriate for the synchronization control is broken when the content of the input stream is subjected to some bit manipulation such as invalid code removal, etc., the above-mentioned method cannot assure the normal operation of the virtual buffer of the T-STD.
Also, when a certain integrated receiver decoder (IRD) is used to simulate each buffer of the T-STD by an IRD for actual operation of the buffer at the transmitting side, it is difficult to have the buffer operate as specified for a memory configuration, inter-memory transfer rate and inter-memory transfer delay.
Accordingly, the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing a multiplexing apparatus and method adapted to assure the normal operation of decoder and code buffer and normal reproduction of decoder.
The above object can be attained by providing a data multiplexer for multiplexing a number n of coded stream data, comprising, according to the present invention:
a number n of means for provisionally storing the number n of coded stream data;
a selection controlling means for retrieving a data occupancy in the number 17 of storage means to select any one of the storage means;
means for switching and delivering the coded stream data from the storage means selected by the selection controlling means;
an output means for multiplexing the switched output from the switching means; and
a virtual storage means for simulating the write and read, for decoding, of the multiplexed bit stream from the output means into and from the code buffer.
In this multiplexer, the selection controlling means selects a data based on a data storage information from the virtual storage means.
Also the above object can be attained by providing a data multiplexer for multiplexing a number n of coded stream data, comprising, according to the present invention:
a number n of means for provisionally storing the number n of coded stream data;
a selection controlling means for retrieving a data occupancy in the number n of storage means to select any one of the storage means;
means for switching and delivering the coded stream data from the storage means selected by the selection controlling means;
an output means for multiplexing the switched output from the switching means; and
means for simulating the write and read, for decoding, of the multiplexed bit stream from the output means into and from the code buffer.
In this multiplexer, the selection controlling means selects a data based on a data storage information from the virtual storage means.
Further, the above objection can be attained by providing a data multiplexing method for multiplexing a number n of coded stream data, comprising, according to the present invention, the steps of:
retrieving the data occupancy in storage units which provisionally store the number n of means to select any one of the storage units;
switching the coded stream data from the selected storage unit to deliver a multiplexed data;
using the multiplexed data to form a multiplexed bit stream; and
simulatively effecting the write and read, for decoding, of the multiplexed bit stream into and from the code buffer to control the selection of the storage units.
Also the above object can be attained by providing a data multiplexing method for multiplexing a number n of coded stream data, comprising, according to the present invention, the steps of:
retrieving the data occupancy in storage units which provisionally store the number n of means to select any one of the storage units;
switching the coded stream data from the selected storage unit to deliver a multiplexed data;
using the multiplexed data to form a multiplexed bit stream; and
simulating the write and read, for decoding, of the multiplexed bit stream into and from the code buffer to control the selection of the storage units.
As mentioned above, the multiplexer according to the present invention comprises means having a virtual code buffer of decoder which is let to operate as specified or means for simulating the change of data occupancy in the code buffer of decoder as specified, and controls the multiplexing while monitoring the operation of the above means from the channel selection controller, thereby assuring the normal operation of the buffer at the decoder side.